A CMOS image sensor can be manufactured by using the same manufacturing processes as a typical CMOS integrated circuit and can be driven with a single power source. In addition, analog circuits or logic circuits using the CMOS processes can be manufactured to coexist in a single chip.
Accordingly, the CMOS image sensor has many advantages such that the number of peripheral ICs can be reduced.
The mainstream of an output circuit of a CCD is a one-channel output type using a FD amplifier having a floating diffusing (FD) layer.
In contrast, the CMOS image sensor includes an FD amplifier for each pixel and the mainstream of the output thereof is a column-parallel output type in which a certain row is selected from a pixel array and pixels of the selected row are simultaneously read in the column direction.
This is because it is difficult to obtain the sufficient driving capability by using the FD amplifiers disposed in the pixels, it is thus necessary to reduce the data rate, and parallel processing is advantageous.
Various circuits have been proposed as a pixel signal reading (output) circuit of the column-parallel output type CMOS image sensor.
One of the most advanced types of circuits is a type in which an analog-digital converter (hereinafter, abbreviated as “ADC”) is provided for each column and pixel signals are obtained as digital signals.
In recent years, high-speed property is widely declared as the directionality of development in the image sensor. On the other hand, a trend of increasing the number of pixels continues as before, and there is a need for developing a sensor in which both the high-speed performance and the increase of the number of pixels are realized.
When a frame rate is improved by skipping pixel signals for realizing high-speed performance in the sensor with a large number of pixels, the exposure amount in each pixel is reduced and the amount of signals is also reduced, therefore, reduction of S/N occurs.
As a solution for the above, the reduction of S/N is prevented by adding pixel signals to be skipped in JP-A-2005-278135 (Patent Document 1).
FIG. 1 is a diagram showing a configuration example of a CMOS image sensor as a solid-state imaging device having an addition unit of pixel signals described in Patent Document 1.
In a solid-state imaging device 10, light incident on the sensor is photoelectrically converted into electric signals by pixels PXL in a pixel array unit 11. In the pixels PXL, a row selection line 13 is selected by a row scanning circuit 12 and pixels PXL-xy are selected in the read row.
Signals for the selected one row are transferred by a vertical signal line 14 to a column processing unit 15 provided at each column.
In a comparator 15-1 inside the column processing unit 15, the signals are compared with a signal from a reference signal generation circuit (DAC) 16 generating a reference signal having a ramp waveform, and an output is inverted by time corresponding to the magnitude of the input signal. Capacitors C1 and C2 for auto-zero or CDS are connected to an input side of the comparator 15-1.
Time until the inversion is counted by a counter 15-2 to thereby generate a digital value.
Furthermore, the digital signals of the column processing unit 15 processed in respective columns by a column scanning circuit 17 are transmitted to a signal processing unit 19 by a horizontal output line 18 and outputted to an output after performing addition/subtraction processing and sorting of data.
Respective operation timings of the above operations are controlled by a timing control circuit 21.
When high-speed imaging is performed in the solid-state imaging device 10, rows to be selected by the row scanning circuit 12 are selected by skipping rows, thereby reducing the data amount per frame finally transmitted to the output 20.
As the data rate at which the signal processing unit 19 performs output is limited, the frame rate can be improved by reducing the data amount.
However, the signal amount accumulated in the pixels PXL is reduced when the frame rate is improved, which lowers S/N. In particular, the reduction of sensitivity will be a problem in recent small pixels.
Accordingly, skipped pixels are added in the solid-state imaging device 10, thereby increasing the signal amount as well as preventing the lowering of S/N.
A solid-state imaging device having another configuration as the adding unit is disclosed in JP-A-2009-212621 (Patent Document 2).
FIG. 2 is a diagram showing a configuration example of a CMOS image sensor as a solid-state imaging device having the addition unit of pixel signals shown in Patent Document 2.
In a solid-state imaging device 10A, timing control is performed, in which whether a counter 15-2 is selectively reset by each column in accordance with a drive mode or not can be determined. The solid-state imaging device 10A further includes a divider so as to change a gradient of a slope having the ramp waveform of a reference signal as an output of the DAC 16.
The following addition is performed as a method of performing addition in the solid-state imaging device 10A.
When a signal from the first pixel is received by column processing units 15a and 15b via the vertical signal line 14, the solid-state imaging device 10A performs addition by counting a value of the second pixel continuously in a state of holing a value of the first pixel without resetting a counter 15-2.
In this method, the data amount horizontally transferred to the signal processing unit 19 is reduced, therefore, high-speed performance can be expected also in the reading mode in which horizontal transfer time is rate-controlled. It is also possible to change weighting on the first pixel and the second pixel by dividing a DAC clock at the time of adding pixels subsequent to the second pixel and changing the slope of the reference signal having the ramp waveform.
When the addition of pixels is simply performed, a false color may be generated as the centroid of signals is irregular according to colors, however, the false color can be suppressed by adjusting the weighting.